The present invention relates to a phase locked loop (PLL) circuit, and more particularly, to a PLL circuit that is preferable for use in a disk apparatus.
In addition to data, clock information is recorded on a recording medium, such as a magnetic disk or an optical disk. Clock information is recorded when the recording medium is formatted or when data is written on the recording medium. With reference to FIG. 1, clock information c may be recorded on the recording medium when the recording medium is manufactured. A spiral recording track 100 is formed on the recording medium. The clock information c is recorded on the track 100 at equal angular intervals.
A disk apparatus, which reads and writes data on a recording medium, includes a PLL circuit 101 as shown in FIG. 2. Referring also to FIG. 1, the PLL circuit 101 multiplies a reference clock signal RC, which is based on the clock information c read from a recording medium 102, by a multiplication ratio N to generate a clock signal CLK. The disk apparatus records data on the recording track 100 from one clock information c to the next clock information c in accordance with the clock signal CLK.
However, if the recording surface is scratched for one reason or another or if the recording surface is smudged, the clock information c may be detected at a location differing from its original position or may not even be detected at all.
Referring to FIG. 3(a), when information similar to the clock information c is recorded at a location that differs from the original position, noise X may be included in the reference clock signal RC and thereby shorten the pulse cycle of the reference clock signal RC. Although only a single pulse of the noise X is shown in FIG. 3(a), a plurality of fine noise pulse signals would actually be included in the reference clock signal RC. Referring to FIG. 3(b), when there is missing clock information c, the pulse cycle of the reference clock signal RC at the location Y where the clock information c is missing becomes long. The cycle of a clock signal CLK generated by such an erroneous reference clock signal RC differs from the cycle of an optimal clock signal CLK generated by a normal clock information c. Accordingly, the PLL circuit 101 requires a long length of time to generate an optimal and stable clock signal CLK from the recorded clock information c. Consequently, an error may occur when data is read or written (read/write error) and the time required to access the disk may increase.